coco-cli_skill

Overview

This skill is a command-line tool for analyzing PCB design files including ODB++ folders and Cadence .brd/.sip files or .out directories. It exposes queries for layers, nets, components, feature measurements, clearance analysis, and PNG rendering to support inspection and DFM checks. The CLI is lightweight and intended for integration into inspection scripts and developer workflows.

How this skill works

The CLI detects input type automatically by inspecting folder structure for ODB++ (matrix/, steps/, misc/) or by recognizing Cadence files and .out directories. It exposes discovery commands (list-layers, list-nets, etc.), measurement commands for feature distances and net clearances, and a render command that produces PNG images of selected layers or nets. Cadence extraction requires a licensed Extracta installation when processing .brd/.sip files.

When to use it

• You have an ODB++ export (directory containing matrix/, steps/, misc/).
• You need to inspect Cadence .brd or .sip files or a Cadence .out directory.
• You want to list layers, nets, components, or export netlists from a PCB design.
• You must measure distances between features or validate net clearances for DFM.
• You need PNG exports of layers or highlighted nets for reports or review.

Best practices

• Always run coco --help and coco <command> --help before using a command to see options.
• Check for an existing coco installation with coco --help before running installers.
• For Cadence files, ensure Extracta is installed and licensed; otherwise use ODB++ input.
• Specify the correct --step when designs contain multiple steps to avoid missing data.
• Use rendering and measurement commands together to visually confirm clearance issues.

Example use cases

• Perform automated DFM clearance sweeps across all nets and export a CSV of violations.
• List all layers and render a selection to PNG for inclusion in a review package.
• Measure minimum distance between a thermal pad and nearby traces to verify spacing.
• Extract component positions and nets to cross-check BOM versus layout connectivity.
• Run a CI job that verifies no short circuits or rule violations before manufacturing.