embedded-systems_skill

This skill helps you develop compact, power-efficient firmware for ARM Cortex-M and ESP32 with RTOS, optimizing timing, memory, and reliability.
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npx veilstrat add skill jeffallan/claude-skills --skill embedded-systems

  • SKILL.md3.9 KB

Overview

This skill provides senior-level embedded systems guidance for firmware development, RTOS integration, and power-optimized designs. It targets microcontrollers like STM32, ESP32, Nordic devices and covers bare-metal and FreeRTOS workflows to produce reliable, resource-efficient firmware.

How this skill works

I inspect your hardware constraints (CPU, memory, peripherals, power budget) and recommend an architecture that balances real-time requirements and resource limits. I produce concrete code patterns: hardware init, HAL drivers, interrupt handlers, and RTOS task structures, plus a concise resource-usage summary and optimization notes. I enforce safety and timing constraints, including watchdogs, short ISRs, and proper synchronization.

When to use it

  • Developing firmware for STM32, ESP32, Nordic, or other MCUs
  • Implementing FreeRTOS or Zephyr tasks, queues, and synchronization
  • Designing or implementing peripheral drivers (I2C, SPI, UART, CAN)
  • Optimizing code size, RAM usage, or battery life for low-power devices
  • Building systems with strict timing, jitter, or real-time guarantees

Best practices

  • Analyze MCU specs and power/timing budgets before coding
  • Keep ISRs short; defer work to tasks or bottom halves
  • Use volatile for hardware registers and avoid unchecked dynamic allocation
  • Add watchdogs, handle all error cases, and document flash/RAM/power usage
  • Use proper synchronization primitives and avoid blocking in ISRs

Example use cases

  • Porting a sensor stack to FreeRTOS with low-power sleep between samples
  • Implementing DMA-driven ADC and SPI drivers with precise timing
  • Reducing firmware footprint for a battery device by removing floating-point ops
  • Designing interrupt-safe communication drivers for CAN or UART
  • Creating a bootloader/OTA flow with safe rollback and resource estimates

FAQ

I profile wake/sleep cycles, minimize peripheral active time, use low-power modes, and reduce CPU frequency or clock gating where possible while tracking trade-offs in latency and jitter.

What do you include in the resource usage summary?

Flash and RAM usage estimates, stack sizes per task, peak current or power estimate, and notes on timing margins and potential bottlenecks.

How are interrupts and synchronization handled?

ISRs are kept minimal; work is queued to RTOS tasks. Shared data uses mutexes or atomic operations and critical sections for short windows, avoiding priority inversion.

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