jump-trading_skill

Overview

This skill codifies Jump Trading–style patterns for building FPGA-accelerated, network-optimized high-frequency trading systems. It focuses on hardware-first designs, wire-to-wire latency measurement, and deterministic, nanosecond-scale execution. Use it to guide FPGA parsers, SmartNIC processing, PTP-based time sync, and topology-driven latency modeling.

How this skill works

The skill inspects design choices across NIC, FPGA, and network layers and recommends concrete patterns: in-hardware market-data parsing and order generation, SmartNIC filtering/ts insertion, and precise hardware timestamping via PTP. It models path latency by breaking down propagation, serialization, switching, and NIC delays, and provides code patterns and measurements to achieve wire-to-wire latency visibility. The guidance emphasizes pipelineable, deterministic logic and end-to-end instrumentation.

When to use it

• Building FPGA-based market-data parsers and order engines that must respond in hundreds of nanoseconds
• Designing network topology where every nanosecond of path latency matters (co-location, microwave links, cut-through switching)
• Implementing hardware timestamping and PTP for nanosecond-accurate measurements across systems
• Offloading filtering and preprocessing into SmartNICs to reduce host CPU latency and jitter
• Validating true wire-to-wire latency and creating automated alerts for slow paths

Best practices

• Prefer deterministic hardware pipelines (FPGA/SmartNIC) for time-critical logic instead of software loops
• Measure wire-to-wire latency using hardware timestamps, not software clocks
• Optimize the full path: propagation, serialization, switching, and NICs — account for medium and routing overhead
• Use cut-through devices and dedicated links; eliminate unnecessary hops and shared infrastructure
• Pipeline processing stages to avoid sequential stalls and minimize jitter

Example use cases

• FPGA module that parses UDP multicast market data and emits orders in a single clock cycle
• Network optimizer that models fiber vs microwave latency and quantifies millisecond savings over long links
• SmartNIC program that filters non-universe market messages, prepends HW timestamps, and drops irrelevant packets on-NIC
• PTP hardware configuration and PHC access code to extract nanosecond RX/TX timestamps for correlation
• Wire-to-wire latency histogramming and alerting to enforce p50/p99/p999 targets